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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 6. Register Address Map
REGISTER
MNEMONIC
SEE
TABLE
C7
C6
COMMAND BITS
C5 C4 C3 C2
C1
C0
HEX CODE
WRITE READ
Channel 1 High Temperature Threshold
Channel 2 High Temperature Threshold
Channel 1 Low Temperature Threshold
Channel 2 Low Temperature Threshold
Channel 1 High Current Threshold
Channel 1 Low Current Threshold
Channel 2 High Temperature Threshold
Channel 2 Low Temperature Threshold
Hardware Configuration
Alarm Software Configuration
Software Configuration
Alarm Hardware Configuration
VSET1
VSET2
APC1 Parameter
APC2 Parameter
DAC1 Input (Write Only)
DAC2 Input (Write Only)
DAC1 Input and Output (Write Only)
DAC2 Input and Output (Write Only)
PGA Calibration Control ( Write Only)
ADC Conversion (Write Only)
Software Shutdown (Write Only)
Load DAC (Write Only)
Message (Write Only)
FIFO
Software Clear (Write Only)
LUT Streaming (Write Only)
Flag (Read Only)
TH1
TH2
TL1
TL2
IH1
IL1
IH2
IL2
HCFIG
ALMSCFIG
SCFIG
ALMHCFIG
VSET1
VSET2
HIST_APC1
HIST_APC2
IDAC1
IDAC2
IODAC1
IODAC2
PGACAL
ADCCON
SSHUT
LDAC
—
—
SCLR
—
—
7
7
8
8
9
9
10
10
11
12
13
14
15
15
16
16
17
17
18
18
19
20
21
22
23
24
25
27
26
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
0
0
0
0
0
0
0
0
0
R W
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
0
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
20
28
22
2A
24
26
2C
2E
30
32
34
36
38
3C
3A
3E
58
5C
5A
5E
60
62
64
66
6E
72
74
7E
—
A0
A8
A2
AA
A4
A6
AC
AE
B0
B2
B4
B6
B8
BC
BA
BE
—
—
—
—
—
—
—
—
—
80
—
—
F6
The following properties of the register address map should be noted:
? All register data is volatile.
? Data stored in locations TH1, TH2, TL1, TL2, IH1, IH2, IL1, IL2, HCFIG, ALMSCFIG, SCFIG, ALMHCFIG, VSET1,
VSET2, IDAC1, IDAC2, IODAC1, IODAC2, PGACAL, ADCCON, SSHUT, and LDAC can be loaded from EEPROM
at power-up or after a full reset.
? Write to the FIFO register only in LUT streaming mode (see the LUT Streaming Mode section).
46
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